1. Field of the Invention
The present invention relates to a field effect transistor using a compound semiconductor, and a method of manufacturing the same.
2. Description of the Prior Art
A field effect transistor using compound semiconductors including GaAs has come to be widely used for a power amplifier, a switch, or the like of wireless communications, especially a cellular phone terminal in recent years. An FET using AlGaAs called PHEMT is commonly used for this GaAs FET (Field Effect Transistor) as a Schottky barrier. When this PHEMT is used in a power amplifier application, due to an increase in a source resistance according to a surface state formed in an AlGaAs layer and a protection film interface beside a gate electrode, and frequency dispersion by charge/discharge of said surface state, sufficient performance cannot be achieved. It is known that this problem will be avoidable by isolating an AlGaAs surface from a channel layer by using a structure called a double recess structure (refer to Japanese Laid-Open Patent Application Publication No. 11-150263). FIG. 16 is a cross-sectional view of an electric field effect type transistor with a conventional double recess structure.
In FIG. 16, there are formed in sequence on a substrate 51 consisting of semi-insulating GaAs: a buffer layer 52 with a thickness of 1 micrometer consisting of undoped GaAs for buffering a lattice mismatch between an epitaxial layer 59 to be grown later, and the substrate 51; a buffer layer 53 consisting of undoped AlGaAs; a channel layer 54 which is consisting of undoped In0.2Ga0.8As with a thickness of 20 nm, and through which a carrier passes; a spacer layer 55 consisting of undoped AlGaAs with a thickness of 5 nm; a carrier supply layer 56 (broken line portion) to which Si being an n-type impurity ion is planar-doped by only 1 atom layer; a Schottky layer 57 consisting of undoped AlGaAs with a thickness of 30 nm; and a cap layer 58 consisting of n+-GaAs with a thickness of 100 nm. Moreover, ohmic electrodes 60 are formed in two areas on the cap layer 58. Herein, a recess is arranged in the Schottky layer 57 consisting of undoped AlGaAs, and a gate electrode 62 is formed so that the recess may be covered. In addition, a device isolation region 61 is formed near the ohmic electrode 60. Moreover, an insulating protective film (not shown) with thin film thickness consisting of SiN or SiO is formed so that exposed surfaces of the gate electrode 62, the Schottky layer 57, and the cap layer 58 may be covered.
The FET with the above conventional double recess structure has a problem as described below.
Although a narrow recess depth of the double recess structure has a correlation with a withstand voltage characteristic between gate-drain electrodes, a second step of the recess structure is made by a single material in a conventional method, so that it will be difficult to control the depth with about several tens of nm, and preferable repeatability will not be obtained. For this reason, a field effect transistor using two types of materials of AlGaAs and InGaP, which have an easy etching control property and have a high selection ratio, is also proposed in Japanese Laid-Open Patent Application Publication No. 9-045894. However, a surface beside the gate electrode is consisting of an InGaP layer in this structure, so that it will be difficult to obtain a sufficient withstand voltage when using in a power amplifier application since a level on the surface of InGaP is few.